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SL74HC533
Octal 3-State Inverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC533 is identical in pinout to the LS/ALS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION SL74HC533N Plastic SL74HC533D SOIC TA = -55 to 125 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output Enable PIN 20=VCC PIN 10 = GND L L L H Latch Enable H H L X D H L X X Output Q L H no change Z
X = don't care Z = high impedance
System Logic Semiconductor
SLS
SL74HC533
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open.
SLS
System Logic Semiconductor
SL74HC533
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 A A V Unit
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA IOUT 7.8 mA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
V
VIL
V
VOH
V
VOL
Maximum Low-Level Output Voltage
VIN= VIL or VIH IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA IOUT 7.8 mA)
IIN IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current
VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0A
ICC
Maximum Quiescent Supply Current (per Package)
6.0
8.0
80
160
A
SLS
System Logic Semiconductor
SL74HC533
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns)
VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay , Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay , Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Latch) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 175 35 30 175 35 30 150 30 26 150 30 26 60 12 10 10 15 85C 220 44 37 220 44 37 190 38 33 190 38 33 75 15 13 10 15 125C 265 53 45 265 53 45 225 45 38 225 45 38 90 18 15 10 15 Unit ns
tPLH, t PHL
ns
tPLZ, t PHZ
ns
tPZL, t PZH
ns
tTLH, t THL
ns
CIN COUT
pF pF
Typical @25C,VCC=5.0 V 37 pF
TIMING REQUIREMENTS(CL=50pF,Input t r=t f=6.0 ns)
VCC Symbol tsu Parameter Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time, Latch Enable to Input D(Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 75 15 13 5 5 5 80 16 14 1000 500 400 85C 95 19 16 5 5 5 100 20 17 1000 500 400 125C 110 22 19 5 5 5 120 24 20 1000 500 400 Unit ns
th
ns
tw
ns
tr, t f
ns
SLS
System Logic Semiconductor
SL74HC533
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
SLS
System Logic Semiconductor
SL74HC533
EXPANDED LOGIC DIAGRAM
SLS
System Logic Semiconductor

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